As integrated circuit device size continues to shrink in order to achieve higher operating frequencies, lower power consumption, and overall higher productivity, fabricating reliable interconnections has become increasingly difficult with respect to both manufacturing and performance.
In order to fabricate a reliable device with a fast operating speed, copper (Cu) is becoming a material of choice for forming the interconnection lines since it has lower electrical resistance compared with that of aluminum and is less prone to electromigration and stress migration.
However, Cu has various shortcomings. For example, Cu has bad adhesive strength to SiO2 and other dielectric materials. Hence, reliable diffusion barriers and adhesion promoters are needed to make copper interconnects feasible. Some currently used interfacial barrier layer materials include tantalum (Ta), tantalum nitride (TaN) and titanium (TiN). When these layers are deposited by conventional methods, they are difficult to form as uniform and continuous layers. This is especially true when the layers to be deposited are less than 10 nanometers thick, and when the layers are formed in high aspect ratio (e.g., depth to width) features such as vias. The Cu/capping layer interface has been known to contribute to electromigration (EM) failure, so optimizing the Cu/cap interface is critical for EM reliability performance. It is therefore desirable to have improved methods for forming copper adhesion promoters and diffusion barriers.